From 298d6d5c4caf70913b397a71b1ff726c04fe1f8e Mon Sep 17 00:00:00 2001
From: dogeystamp <dogeystamp@disroot.org>
Date: Thu, 4 Jan 2024 22:29:34 -0500
Subject: [PATCH] implemented register getter/setter

---
 .gitignore  |   1 +
 Cargo.lock  |   7 ++++
 Cargo.toml  |   8 ++++
 src/main.rs | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 126 insertions(+)
 create mode 100644 .gitignore
 create mode 100644 Cargo.lock
 create mode 100644 Cargo.toml
 create mode 100644 src/main.rs

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..ea8c4bf
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+/target
diff --git a/Cargo.lock b/Cargo.lock
new file mode 100644
index 0000000..7efd4bd
--- /dev/null
+++ b/Cargo.lock
@@ -0,0 +1,7 @@
+# This file is automatically @generated by Cargo.
+# It is not intended for manual editing.
+version = 3
+
+[[package]]
+name = "lc3"
+version = "0.1.0"
diff --git a/Cargo.toml b/Cargo.toml
new file mode 100644
index 0000000..5e00ea8
--- /dev/null
+++ b/Cargo.toml
@@ -0,0 +1,8 @@
+[package]
+name = "lc3"
+version = "0.1.0"
+edition = "2021"
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
diff --git a/src/main.rs b/src/main.rs
new file mode 100644
index 0000000..138aa3b
--- /dev/null
+++ b/src/main.rs
@@ -0,0 +1,110 @@
+#![allow(dead_code)]
+#![allow(unused_variables)]
+
+const MEM_SIZE: usize = 1 << 16;
+const PC_START: usize = 0x3000;
+
+enum OpCodes {
+    // branch
+    BR = 0,
+    // add
+    ADD,
+    // load
+    LD,
+    // store
+    ST,
+    // jump register
+    JSR,
+    // bitwise and
+    AND,
+    // load register
+    LDR,
+    // store registerj
+    STR,
+    // return from interrupt (unused)
+    RTI,
+    // bitwise not
+    NOT,
+    // load indirect
+    LDI,
+    // store indirect
+    STI,
+    // jump
+    JMP,
+    // reserved (unused)
+    RES,
+    // load effective address
+    LEA,
+    // trap
+    TRAP,
+}
+
+struct Registers {
+    r0: u16,
+    r1: u16,
+    r2: u16,
+    r3: u16,
+    r4: u16,
+    r5: u16,
+    r6: u16,
+    r7: u16,
+    pc: u16,
+    cond: u16,
+    count: u16,
+}
+
+impl Registers {
+    fn new() -> Registers {
+        Registers {
+            r0: 0,
+            r1: 0,
+            r2: 0,
+            r3: 0,
+            r4: 0,
+            r5: 0,
+            r6: 0,
+            r7: 0,
+            pc: PC_START as u16,
+            cond: 0,
+            count: 0,
+        }
+    }
+
+    fn register_reference(&mut self, idx: u16) -> &mut u16 {
+        match idx {
+            0 => &mut self.r0,
+            1 => &mut self.r1,
+            2 => &mut self.r2,
+            3 => &mut self.r3,
+            4 => &mut self.r4,
+            5 => &mut self.r5,
+            6 => &mut self.r6,
+            7 => &mut self.r7,
+            8 => &mut self.pc,
+            9 => &mut self.cond,
+            _ => panic!("Invalid register {}", idx),
+        }
+    }
+
+    fn set_reg(&mut self, idx: u16, val: u16) {
+        *self.register_reference(idx) = val;
+    }
+
+    fn get_reg(&mut self, idx: u16) -> u16 {
+        let reg = &*self.register_reference(idx);
+        *reg
+    }
+}
+
+struct VM {
+    mem: [u16; MEM_SIZE]
+}
+
+fn main() {
+    println!("Hello, world!");
+
+    let mut regs = Registers::new();
+    println!("was {}", regs.get_reg(0));
+    regs.set_reg(0, 3);
+    println!("set to {}", regs.get_reg(0));
+}