From 4ee0822e58cd582e5a06037d3a4973b11a651e3e Mon Sep 17 00:00:00 2001
From: dogeystamp <dogeystamp@disroot.org>
Date: Sat, 6 Jan 2024 16:37:00 -0500
Subject: [PATCH] opcode: BR

---
 src/vm/instruction.rs | 15 +++++++++++++--
 src/vm/mod.rs         |  2 +-
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/vm/instruction.rs b/src/vm/instruction.rs
index ee18e55..86cf402 100644
--- a/src/vm/instruction.rs
+++ b/src/vm/instruction.rs
@@ -73,7 +73,7 @@ pub fn execute_instruction(vm: &mut VM, instr: u16) {
     let opcode = get_opcode(instr);
 
     match opcode {
-        OpCode::BR => todo!("BR"),
+        OpCode::BR => op_br(vm, instr),
         OpCode::ADD => op_add(vm, instr),
         OpCode::LD => op_ld(vm, instr),
         OpCode::ST => op_st(vm, instr),
@@ -142,7 +142,7 @@ fn op_ldr(vm: &mut VM, instr: u16) {
 }
 
 ////////////////
-// Jumps
+// Jumps/branches
 ////////////////
 
 fn op_jsr(vm: &mut VM, instr: u16) {
@@ -158,6 +158,17 @@ fn op_jsr(vm: &mut VM, instr: u16) {
     }
 }
 
+fn op_br(vm: &mut VM, instr: u16) {
+    let offset = sign_extend(instr & 0x1ff, 9);
+    // technically the COND we have is just a part of the PSR register in the spec
+    // therefore isolate the last 3 bits
+    let cond = vm.registers.cond & 0x7;
+
+    if (instr >> 9) & 0x7 & cond != 0 {
+        vm.registers.pc = vm.registers.pc.wrapping_add(offset);
+    }
+}
+
 ////////////////
 // Store ops
 ////////////////
diff --git a/src/vm/mod.rs b/src/vm/mod.rs
index 43594fd..efbe191 100644
--- a/src/vm/mod.rs
+++ b/src/vm/mod.rs
@@ -18,7 +18,7 @@ mod instruction;
 ////////////////
 
 // condition flags (COND register)
-enum CondFlags {
+pub enum CondFlags {
     // positive (P)
     POS = 1 << 0,
     // zero (Z)