diff --git a/src/vm/instruction.rs b/src/vm/instruction.rs index 316dc5a..63e7d28 100644 --- a/src/vm/instruction.rs +++ b/src/vm/instruction.rs @@ -4,6 +4,7 @@ use crate::vm::VM; +#[derive(Debug)] enum OpCode { // branch BR = 0, @@ -44,23 +45,23 @@ enum OpCode { fn get_opcode(instruction: u16) -> OpCode { // the opcode is stored in the left 4 bits match instruction >> 12 { - 0 => OpCode::BR, - 1 => OpCode::ADD, - 2 => OpCode::LD, - 3 => OpCode::ST, - 4 => OpCode::JSR, - 5 => OpCode::AND, - 6 => OpCode::LDR, - 7 => OpCode::STR, - 8 => OpCode::RTI, - 9 => OpCode::NOT, + 0 => OpCode::BR, + 1 => OpCode::ADD, + 2 => OpCode::LD, + 3 => OpCode::ST, + 4 => OpCode::JSR, + 5 => OpCode::AND, + 6 => OpCode::LDR, + 7 => OpCode::STR, + 8 => OpCode::RTI, + 9 => OpCode::NOT, 10 => OpCode::LDI, 11 => OpCode::STI, 12 => OpCode::JMP, 13 => OpCode::RES, 14 => OpCode::LEA, 15 => OpCode::TRAP, - _ => OpCode::NOOP, + _ => OpCode::NOOP, } } @@ -69,21 +70,21 @@ pub fn execute_instruction(vm: &mut VM) { let opcode = get_opcode(instruction); match opcode { - OpCode::BR => no_op(vm), - OpCode::ADD => no_op(vm), - OpCode::LD => no_op(vm), - OpCode::ST => no_op(vm), - OpCode::JSR => no_op(vm), - OpCode::AND => no_op(vm), - OpCode::LDR => no_op(vm), - OpCode::STR => no_op(vm), - OpCode::RTI => no_op(vm), - OpCode::NOT => no_op(vm), - OpCode::LDI => no_op(vm), - OpCode::STI => no_op(vm), - OpCode::JMP => no_op(vm), - OpCode::RES => no_op(vm), - OpCode::LEA => no_op(vm), + OpCode::BR => no_op(vm), + OpCode::ADD => no_op(vm), + OpCode::LD => no_op(vm), + OpCode::ST => no_op(vm), + OpCode::JSR => no_op(vm), + OpCode::AND => no_op(vm), + OpCode::LDR => no_op(vm), + OpCode::STR => no_op(vm), + OpCode::RTI => no_op(vm), + OpCode::NOT => no_op(vm), + OpCode::LDI => no_op(vm), + OpCode::STI => no_op(vm), + OpCode::JMP => no_op(vm), + OpCode::RES => no_op(vm), + OpCode::LEA => no_op(vm), OpCode::TRAP => no_op(vm), OpCode::NOOP => no_op(vm), }