opcode: BR

src/vm/instruction.rs

@@ -73,7 +73,7 @@ pub fn execute_instruction(vm: &mut VM, instr: u16) {
     let opcode = get_opcode(instr);
 
     match opcode {
-        OpCode::BR => todo!("BR"),
+        OpCode::BR => op_br(vm, instr),
         OpCode::ADD => op_add(vm, instr),
         OpCode::LD => op_ld(vm, instr),
         OpCode::ST => op_st(vm, instr),
@@ -142,7 +142,7 @@ fn op_ldr(vm: &mut VM, instr: u16) {
 }
 
 ////////////////
-// Jumps
+// Jumps/branches
 ////////////////
 
 fn op_jsr(vm: &mut VM, instr: u16) {
@@ -158,6 +158,17 @@ fn op_jsr(vm: &mut VM, instr: u16) {
     }
 }
 
+fn op_br(vm: &mut VM, instr: u16) {
+    let offset = sign_extend(instr & 0x1ff, 9);
+    // technically the COND we have is just a part of the PSR register in the spec
+    // therefore isolate the last 3 bits
+    let cond = vm.registers.cond & 0x7;
+
+    if (instr >> 9) & 0x7 & cond != 0 {
+        vm.registers.pc = vm.registers.pc.wrapping_add(offset);
+    }
+}
+
 ////////////////
 // Store ops
 ////////////////

src/vm/mod.rs

@@ -18,7 +18,7 @@ mod instruction;
 ////////////////
 
 // condition flags (COND register)
-enum CondFlags {
+pub enum CondFlags {
     // positive (P)
     POS = 1 << 0,
     // zero (Z)